This invention relates to a semiconductor circuit for driving a load circuit with a relatively large load capacity by using a signal which is formed by amplifying and wave-shaping a small input signal.
In integrated circuits for high frequency pulse signals e.g. video signals of several MHz, a sine or triangle wave signal with relatively small amplitude is used for the clock signal. In the integrated circuit (IC) receiving such a small amplitude clock signal, a predetermined DC bias voltage is applied to the input clock signal, and the biased clock signal is input to a wave shaper circuit. The wave shaper circuit amplifies and wave shapes the clock signal into a rectangular or trapezoidal wave signal with such an amplitude as to operate the driver circuit at the next stage. The wave shaped pulse signal is input to the driver circuit, which in turn converts it into a clock pulse signal with an amplitude large enough to drive a load circuit on the IC chip, with a large load capacity such as wiring capacities. This clock pulse signal is input to the load circuit to control the operation thereof.
Since the wave shaper circuit and the driver circuit are arranged in successive stages, and the IC chip area should be effectively used, a power supply line of a reference potential (ground potential) and a power supply line of a power source potential are commonly connected to the wave shaper circuit and the driver circuit for operating the circuits.
FIG. 1 shows a block diagram illustrating a configuration of the prior integrated circuit which includes a wave shaper circuit, a driver circuit and others. In the figure, reference numeral 100 denotes a bonding pad for signal input, which is coupled with a sine or triangular wave signal with a small amplitude as a clock signal. Reference numeral 101 denotes a wave shaper circuit. Numeral 102 denotes a driver circuit. Numeral 103 denotes a bias generator circuit for generating a DC bias voltage to be applied to the input clock signal. The DC bias voltage generated by bias generator circuit 103 is applied to pad 100 via resistor 110. 104 denotes a bonding pad for supplying the power source potential Vcc. 105 denotes a bonding pad for supplying the reference potential (ground potential GND).
The power source potential Vcc supplied to pad 104 is supplied to wave shaper circuit 101 and driver circuit 102 via common wiring 106, and is also supplied to bias generator circuit 103 via wiring 107. The reference potential GND supplied to pad 105 is supplied to wave shaper circuit 101 and driver circuit 102 via common wiring 108, and is also supplied to bias generator circuit 103 via wiring 109.
The final stage circuit of driver circuit 102 has a configuration shown in FIG. 2, for example. Reference numeral 121 denotes a P channel MOS transistor. Numeral 122 denotes an N channel MOS transistor. The source of transistor 121 is connected to power source potential Vcc. The source of transistor 122 is connected to the reference potential GND. The gates of transistors 121 and 122 are connected with each other. A pulse signal is supplied at the connection point of the bases of transistor 121 and 122. Load capacitance 123 is connected between the connection point of its drains of transistors 121 and 122 and the reference potential GND. The load capacitance 123 equivalently represents the load capacitance of a load circuit driven by an output clock pulse signal of driver circuit 102. Since it is necessary for driver circuit 102 to drive a relatively large load capacitance, transistors 121 and 122 are designed so as to have relatively large sizes.
The instantaneous AC current Iac flowing into the final stage circuit when the pulse signal is input to driver circuit 102 is given by the following expression EQU Iac=f.multidot.C.multidot.V (1)
where f represents the frequency of the output clock pulse signal of the final stage circuit, C represents the value of load capacitance 123, and V represents the value of the power source potential Vcc. As seen from the expression (1), as f and/or C increases, instantaneous AC current Iac flowing into the final stage of driver circuit 102 increases.
FIG. 3 shows an equivalent circuit of wave shaper circuit 101 and driver circuit 102 in the integrated circuit of FIG. 1, as viewed from reference potential supplying pad 105. As shown in the figure, resistance r1 and inductance l1 parasitic to wiring 108 are connected in series between wave shaper circuit 101 and driver circuit 102. Resistance r2 and inductance l2 parasitic to wiring 108 are connected in series between driver circuit 102 and pad 105. These resistances r1 and r2 and inductances l1 and l2 are connected in series between wave shaper circuit 101 and pad 105. Instantaneous AC current Iac as given by expression (1) flows into resistance r2 and inductance l2 connected between pad 105 and driver circuit 102, and, consequently, the potential of wiring 108 varies at fixed periods as determined by the fundamental wave component and the harmonic components of the instantaneous AC current. Therefore, when the integrated circuit in FIG. 1 is operated with relatively small amplitude signals, the operating point of the wave shaper circuit 101 shifts due to the potential variation in wiring 108, possibly resulting in erroneous operation of the integrated circuit.
One of the approaches to cope with this problem is to increase the amplitude of the pulse signal to be input to pad 100. In such a case, the integrated circuit necessarily handles a high amplitude signal. However, such signal creates another problem of cross talk of the pulse signal to other circuits assembled on the same semiconductor chip.
Another approach, which may have potential, is to widen the width of reference potential wiring 108, to reduce the wiring impedance. To reduce the wiring impedance to a satisfactory degree, however, the width of wiring 108 must be significantly widened. This leads to an undesirable increase of the pattern area on the semiconductor chip, and hinders the improvement of the package density of IC chips.
The above approaches, which have been described in connection with the reference potential wiring, can also be applied to the power source potential wiring.
As described above, the prior art semiconductor circuit for driving a load circuit can not handle large amplitude pulse signals. Also the semiconductor circuit can not accept the widening of power wiring. Therefore, the reference potential and/or power source potential vary due to the instantaneous AC current flowing through the driver circuit. Thus, the prior art semiconductor circuit involves erroneous operation problems due to the potential variation.